1. Field of the Invention
The present invention relates to a serial data receiver, and particularly, to an asynchronous serial data receiver for packet transfer.
2. Description of Related Art
FIG. 5 shows a serial data receiver according to a related art. This serial data receiver has a differential receiver 201, a tracking unit 203 coupled to an output terminal of the differential receiver 201, a memory 204 coupled to an output side of the tracking circuit 203, and a phase-locked oscillator 202 coupled to the tracking circuit 203 and FIFO 204.
According to the serial data receiver of the related art shown in FIG. 5, an input terminal 251 receives an input signal S1 and an input terminal 252 receives an input signal S2. Upon receiving the input signals S1 and S2, the differential receiver 201 provides, from the output terminal thereof, received serial data RX that is a differential signal of the two input signals S1 and S2. The oscillator 202 provides a phase-stabilized clock signal CKR. The tracking circuit 203 receives the clock signal CKR and received serial data RX and provides a synchronous clock signal CKW and serial data DX. The synchronous clock signal CKW is formed by tracking the clock signal CKR with the received serial data RX. In response to transition in the synchronous clock signal CKW, the FIFO 204 stores the serial data DX in an internal register, and at the same time, counts up a write address pointer. Then, in synchronization with the clock signal CKR, the FIFO 204 provides the stored data to an output terminal 253 and counts up a read address pointer.
FIG. 6 is a timing chart showing the operation of the serial data receiver according to the related art. The serial data receiver of FIG. 5 employing the differential data transfer technique sometimes causes ringing noise between time T100 and T101 when the two input signals S1 and S2 shift from an opposite-phase state to an in-phase state. The ringing noise may affect to the received serial data RX as shown in FIG. 6. For instance, the ringing noise may be overlaid on the received serial data RX. With the noise-overlaid received serial data RX, the tracking circuit 203 may provide a narrow clock signal having narrow pulse intervals as shown in FIG. 6. Since the write address counter of the FIFO 204 conducts a count-up operation based on the synchronous clock signal CKW, the narrow clock signal may cause a malfunction of the write address counter. More precisely, there will be an error between data to be stored and a write address pointer value, so that the write address pointer may point a wrong position in the FIFO 204.